The present invention relates to optimizing the design and manufacturing of integrated circuits (also known as xe2x80x98IC chipsxe2x80x99 or xe2x80x98chipsxe2x80x99). It describes a method for allowing the IC design engineer to optimize the dimensions of an IC for manufacturing. It also allows a wafer fab engineer to optimize output or throughput of optical printing systems used in manufacturing ICs.
In the past there has been very little improvement in the area of interaction between the design, manufacturing, and packaging of the IC chips. It has been realized that inefficient IC design can reduce throughput in the manufacturing of the IC by 60% or more. It has been recognized that for some IC designs, a slightly different chip size or aspect ratio can result in significantly better manufacturing throughput. There are very few tools available to the designer of ICs to determine the IC chip size (X and Y dimensions) that optimizes manufacturability. These programs or tools are most effectively used early in the design cycle when the designer can more easily modify the IC chip size. Similarly, very few tools are available to the wafer fab engineer to optimize the use of an existing reticle when printing wafers. The existing tools have several limitations:
Representation of reticle layout is often limited or inaccurate.
Tools are often designed to meet the needs of one and only one wafer fab.
Wafer fab optimization criteria are often inflexible and cannot be adjusted to address changing engineering or business requirements.
When generating shot maps (description of how a reticle is used to print chips on a wafer), many of these tools produce significantly sub-optimal results.
Most of these tools have no knowledge of packaging/assembly constraints.
The inaccuracies above prevent the IC designer, planner or sales engineer from getting reliable estimates of chips per wafer for a given IC design.
When determining the optimal chip size, existing tools explore a range of possible chip sizes by covering the space with an evenly distributed matrix of sample points. To explore a large region of possible chip sizes using these tools, a correspondingly large number of sample points are required, utilizing excessive compute resources. This results in severe tradeoffs between the range of chip sizes explored, accuracy of the results, and compute resources/run time. In addition, the existing tools make simplifying assumptions about the frame (scribe) around the chip. A typical, though often inaccurate, simplifying assumption is that the frame x and y dimensions are constant across the entire range of possible chip sizes. Finally, the existing tools do not have the capability to automatically explore the impact of rotating the chip on the reticle and or the wafer.
In order to maximize the number of good chips printed on a wafer it is critical that the optimal position of the integrated circuit reticle (photomask) with respect to the wafer is determined. This is the chip-to-wafer offset. Existing tools determine this offset by dividing the range of possible chip-to-wafer offsets into a regularly spaced matrix of points which are then each examined. There is a major weakness with this approach.
Packing chips onto a wafer is a discrete optimization problem; there are a large number of local maxima. The common xe2x80x98matrixxe2x80x99 method offers no guarantee that a better chip-to-wafer offset does not happen to fall between two offsets that are examined.
To compensate for the weakness above, one must sweep the range of allowed chip-to-wafer offsets using very small steps. This creates a very large matrix of prospective offsets to examine. The required computation places severe limits on how broad a set of parameters can be explored. To minimize the use of compute resources, sacrifices are often made in the quality of the solution.
The instant invention is a method and system for optimizing the size of an IC chip and the number of IC chips obtainable from a wafer. The system integrates:
(a) a chip size optimization and visualization sub-system (contour plot)
(b) a frame (scribe) generation sub-system (reticle layout)
(c) a shot map optimization sub-system (wafer layout)
Integration of these three sub-systems provides an efficient and optimal solution for both:
IC designers optimizing the size of the chip
Wafer fab engineers optimizing either output or throughput on an optical printing system
The chip size optimization sub-system uses a computationally efficient xe2x80x98divide-and-conquerxe2x80x99 method to explore the range of possible chip sizes. This allows a large range of possible chip sizes to be explored without excessive compute resources and run time.
The frame generation sub-system uses a method that determines the exact dimensions of the frame and the exact number and arrangement of chips on the reticle for a particular chip size, wafer fab and manufacturing process. This significantly enhances the accuracy of the chip size optimization results.
The shot map optimization sub-system can optimize the output or throughput of the wafer fab optical printing system. The wafer fab may choose to optimize outputxe2x80x94measured in chips per wafer (CPW). Alternatively, the wafer fab may choose to optimize throughputxe2x80x94measured in chips per hour (CPH)xe2x80x94achieving a balance between the number of chips on the wafer versus the manufacturing resources required to produce them. Shot map optimization is performed in a computationally efficient manner, allowing a large number of options to be explored without excessive compute resources or run time.
These and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.